DFT Engineer, Automotive Robotics

Kurz zusammengefasst

Tenstorrent, a leader in cutting‑edge AI technology, is expanding its Automotive Robotics team. The company builds high‑performance RISC‑V CPUs and AI accelerators, and now seeks a DFT Engineer to design and deliver core hardware modules for its next‑generation chiplet‑based system‑on‑chips (SoCs) aimed at automotive applications. The role is remote but based in Munich, Germany, and welcomes candidates at various seniority levels, with offers matched to the appropriate experience. In this position you will define the design‑for‑test (DFx) strategy for multi‑chiplet packages, guiding the process from architecture through high‑volume production. Daily tasks include using industry‑standard ATPG and DFx insertion CAD tools, writing RTL for DFx logic such as lock‑up latches, clock gates and scan anchors, and converting system and safety requirements into concrete constraints on package architecture and test plans. You will also plan, implement and verify MBIST, LBIST and IST, as well as integrate JTAG, scan compression and ASST features, while performing ATPG and test‑coverage analysis. The role requires extensive experience: at least ten years of work across multiple teams and companies coordinating test, yield and quality efforts, deep familiarity with fault models (stuck‑at, transition, gate‑exhaustive, path‑delay, IDDQ, cell‑aware), and proven competence with the CAD tools and RTL coding mentioned above. Candidates must be able to translate safety specifications into DFT constraints and support test engineering through planning, pattern generation and debugging. Additional assets include exposure to post‑silicon testing and tester‑pattern debug, as well as experience running fault campaigns. The position offers a highly competitive compensation package, equal‑opportunity employment, and the chance to learn how to bring a SiP to automotive‑grade, high‑volume production while balancing package architecture, DFT and test cost. Employment is contingent on compliance with U.S. export‑control regulations. What the role asks for: - Experience with industry‑standard ATPG and DFx insertion CAD tools - Fluent RTL coding for DFx logic (lock‑up latches, clock gates, scan anchors) - Ability to translate system and safety requirements into DFT constraints - Knowledge of fault models: stuck‑at, transition, gate‑exhaustive, path‑delay, IDDQ, cell‑aware - Ten or more years coordinating test, yield and quality across teams - MBIST, LBIST, IST planning, implementation and verification - JTAG, scan compression and ASST implementation experience - ATPG and test‑coverage analysis using industry tools - Nice‑to‑have: exposure to post‑silicon testing and pattern debug - Nice‑to‑have: experience with fault campaigns